VLSI SoC Design using Verilog HDL

ASAP Kerala conducted a 3-day online VLSI SoC Design workshop using Verilog HDL with Maven Silicon, Bengaluru, from 24 February to 26 February, 2024. This initiative aligns with ASAP Kerala’s Smart Learn project, aimed at acquainting students with the latest advancements and technologies in their respective fields. With over 2000 students registered, the workshop has drawn significant interest from students seeking to explore the details of VLSI SoC design utilising Verilog HDL. The workshop provided invaluable insights and hands-on experience in the field of VLSI as the session proved to be an exciting opportunity for students from electronics and electrical stream to enhance their technical capabilities and explore career avenues in VLSI chip design. Upon completion of the workshop, 777 students were provided a joint certificate from ASAP Kerala and Maven Silicon.